This application claims priority from Korean Patent Application No. 1999-24023, filed on Jun. 24, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device and, more particularly, to a block architecture option circuit for nonvolatile semiconductor memory devices.
In general, semiconductor memory devices for storing data are classified into volatile memory devices such as DRAM (dynamic random access memory) and SRAM (static random access memory), and nonvolatile memory devices such as PROM (programmable read only memory), EPROM (erasable programmable read-only memory), EEPROM (electrically erasable and programmable read-only memory), and FRAM (ferroelectric random access memory device). Volatile memory devices lose stored data at power-off, but nonvolatile memory devices maintain stored data even after power-off. Therefore, high-density nonvolatile memory devices, in particular, flash EEPROM devices have been widely applied to various fields such as computer systems and digital handy terminals. Due to high programming speed and low power consumption, the flash EEPROM device can be used as a BIOS-ROM (basis input/output system-read-only memory) in personal computer systems and large-amount storing media of integration circuit cards for digital cameras and personal computers. Systems having nonvolatile memories are disclosed in U.S. Pat. No. 5,461,646 and U.S. Pat. No. 5,568,641. Further, a personal computer system using a flash memory as a BIOS-ROM is disclosed in U.S. Pat. No. 5,473,775.
A flash memory cell includes a field effect transistor having a control gate, a floating ate, a source, and a drain. The charge on the floating gate is changed to change the threshold voltage of a flash cell, storing data in the flash cell.
From a standpoint of a memory cell structure, flash EEPROM devices are classified into NAND-type devices and NOR-type devices. A memory of a NAND structure requires one contact per one unit (i.e., string) where a plurality of cells are connected in series. In a memory of a NOR structure, each cell is independently coupled to a bit line and a word line, reducing interruptions caused by other cells during the write or read operation of any cell. Having a relatively large cell current, the memory of a NOR structure can be operated with high speed in comparison with the memory of a NAND structure.
The newest high-integrated NOR flash EEPROM devices adopt a cell array architecture, which is divided into a number of unit regions. That is, bulk and cell transistors are divided into a plurality of sectors or blocks and sources of the cell transistors in a block are connected to a corresponding divided bulk in common. This structure enables all cells in a block to be erased at the same time. Generally, the NOR flash EEPROM devices are programmed with a unit of 1 byte (=8 bits) or 1 word (=16 bits).
In a NOR flash memory device, there are normal blocks for storing normal data and boot (or parameter) blocks. Each of the normal blocks has a size of 64 Kbytes (=32 Kwords). The boot blocks have various sizes such as 32 Kbytes (=16 Kwords), 16 Kbytes (=8 Kwords), and 8 Kbytes (=4 Kwords). These boot blocks are disclosed in U.S. Pat. No. 5,701,492.
A boot block of a nonvolatile semiconductor memory is used to store a relatively small amount of information, such as BIOS code data or a password of a computer or a digital handy terminal system. At power-up, a CPU (central processing unit) of a system accesses the boot block in the first place. Compared with normal blocks, erasing and programming operations of the boot block are more frequently performed.
Based on the address coding of a CPU, a cell array block architecture of a nonvolatile semiconductor memory device is generally divided into a top boot block architecture and a bottom boot block architecture.
FIG. 1A shows a top boot block architecture of a memory cell array 100 in accordance with the prior art. In the top boot block architecture, boot blocks B_BLK0-B_BLKm are disposed in a higher order address region and normal blocks N_BLK0-N_BLKn are disposed in a lower order address region. When a system is powered up, a CPU supplies the highest block address for the first boot block B_BLK0 to a nonvolatile memory device, and reads boot codes required for initialization of the system from the first boot block B_BLK0. Then, the CPU accesses the block addresses according to a predetermined order and reads boot codes stored in the other boot blocks B_BLK1-B_BLKm.
FIG. 1B shows a bottom block architecture of a memory cell array 100 in accordance with a prior art. In the bottom boot block architecture, boot blocks B_BLK0-B_BLKm are disposed in a lower order address region and normal blocks are disposed in a higher order address region. When a system is powered up, a CPU supplies the lowest block address for the first boot block B_BLK0 to a non-volatile memory device, and reads boot codes required for initialization of the system from the first boot block B_BLK0. Then, the CPU accesses the block addresses according to a predetermined order and reads boot codes stored in the other boot blocks B_BLK1-B_BLKm.
In order to meet requirements for the two kinds of block architecture options, a metal layer option method is utilized in the prior art.
FIG. 2 is a block diagram showing a cell array 100, a block address buffer circuit 210, and a block selection circuit 220 of a nonvolatile semiconductor memory device using the metal layer option method in accordance with the prior art. Referring now to FIG. 2, the block address buffer circuit 210 comprises a NOR gate circuit 211, inverter gate circuits 212, 213, 217, and 218, and metal wirings 215, 216a, and 216b. The NOR gate circuit 211 receives an external block address Axi and a chip enable signal {overscore (CE)} to generate an internal block address signal Ai. A block selection circuit 220 responses to the internal block address Ai to select a corresponding block in the memory cell array 100.
In a conventional metal layer option method, a nonvolatile semiconductor memory device is designed on the basis of one of the top and the bottom boot block architectures. Then, according to requirement of a user, an inverter gate circuit 214 is added to or separated from a block address buffer circuit 210. If the memory device is designed to have the top boot block architecture, the inverter gate circuit 214 is not required in the block address buffer circuit 210 of FIG. 2. Therefore, metal wiring 215 between inverter gate circuits 213 and 217 is formed and other metal wirings 216a and 216b are not formed. If a user requires the memory device to have the bottom boot block architecture, the inverter gate circuit 214 should be added to the block address buffer circuit 210. In this case, the metal wiring 216a between the inverter gate circuits 213 and 214, and the metal wiring 216b between the inverter gate circuits 214 and 217 should be formed while the metal wiring 215 between the inverter gate circuits 213 and 217 should not be formed. Because polarity of an output signal Ai of the block address buffer circuit 210 is inverted in the bottom boot block architecture, the decoding order of a block address will be the reverse of that of the top boot block architecture.
These cell array block options can be supplied to a user utilizing metal masks or reticles, which are different from each other, in the final fabrication stage. A nonvolatile semiconductor memory device such as a conventional NOR flash memory supports a variety of package options. If cell array options meeting the requirements of a user are added thereto, the number of the metal reticles will be twice as many as without the additional requirements. This leads to increase in device production cost.
It is an object of the invention to provide a nonvolatile memory device which can solve the foregoing problems.
It is another object of the invention to provide a block option circuit which is capable of making a nonvolatile semiconductor memory device selectively supply one of the block architecture options of a cell array without requiring a metal layer option method.
According to the invention, a nonvolatile semiconductor memory device comprises a memory cell array, a block address input circuit, and a block selection circuit. The memory cell array includes a plurality of normal blocks for storing normal data, and a plurality of boot blocks for storing boot codes to initialize a system in which a memory device of this invention is used. The nonvolatile semiconductor memory device of this invention supports a plurality of boot block architecture options for user selection. The block address input circuit includes means for storing block architecture information indicating one of the boot block architecture options, and converts an external block address into an internal block address in accordance with the stored boot block architecture information. Converting the block address by the block address input circuit is controlled by the stored block architecture information. The block selection circuit selects one of blocks of the memory cell array in response to an internal block address supplied from the block address input circuit.
In a preferred feature of the invention, a block address input circuit includes option selection means having a pair of terminals. The option selection means is composed of, for example, one fuse or a pair of pad terminals and a bonding wire. Selecting one of boot block architecture options is determined by terminal-to-terminal electrical connection/disconnection of the option selection means.
In another preferred feature of the invention, a memory cell array is divided into a top address region and a bottom address region. The memory cell array includes a top boot block architecture option and a bottom boot block architecture option, which arrange boot blocks in the top and the bottom address regions, respectively. If a nonvolatile memory device utilizing the invention has the top boot block architecture option, an internal block address is identical to an external block address. On the other hand, if the nonvolatile memory device has the bottom boot block architecture option, the internal block address is different from the external block address.
In another preferred feature of the invention, a nonvolatile semiconductor memory device comprises a memory cell array, a power supply voltage detection circuit, an option flag circuit, a block address buffer circuit, and a block selection circuit. The detection circuit detects the power supply voltage and generates a detection signal when the power supply voltage reaches a predetermined level. The option flag circuit generates a flag signal indicating one of a plurality of boot block architecture options in response to the detection signal. The address buffer circuit receives an external block address, and converts the external block address into an internal block address in response to the flag signal. The block selection circuit selects a corresponding block in the memory cell array in response to the internal block address. The option flag circuit includes option selection means having a first and a second terminals. A nonvolatile memory device based on this embodiment has one of the boot block architectures in accordance with the connection/disconnection of the first terminal to the second terminal. If the first terminal is electrically connected to the second terminal, the nonvolatile memory device has a top boot block architecture option. On the other hand, if the first terminal is electrically insulated from the second terminal, the nonvolatile memory device has a bottom boot block architecture option. In the nonvolatile memory device, the option selection means can be implemented by at least one fuse or at least one pair of pad terminals and a bonding wire.
In another preferred feature of the invention, a block address input circuit converting an external block address into an internal block address comprises at least one nonvolatile memory cell. Block architecture information is stored in the nonvolatile memory cells. Converting the block address by the block address input circuit is controlled by the stored block architecture information.
In another preferred feature of the invention, block architecture information is stored in at least one of cell of a memory cell array. Converting the block address by the block address input circuit is controlled by the stored block architecture information.
In another preferred feature of the invention, a nonvolatile semiconductor memory device comprises a memory cell array having top and bottom block architecture options; an option plug circuit having a pair of pad terminals, an input terminal connected to these terminals in common, and an output terminal for outputting a flag signal indicating one of the boot block architecture options; a block address buffer circuit receiving external block address and converting the external address into the internal block address in response to the flag signal; and a block selection circuit selecting corresponding one of the blocks of the memory cell array in response to the internal block address. One of the boot block architecture options is determined by connecting one of a pair of the pad terminals to one of power supply voltage and ground voltage.